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EM MICROELCTRONIC-MARIN SA
V6123
Digitally Programmable 2, 4 and 8 Mux LCD Driver
Features
n n n n n n n n n n n n n n n n
Typical Operating Conditions
Very simple 1-bit interface (see Fig. 1) V6123 mux mode 2 with 2 rows and 58 columns V6123 mux mode 4 with 4 rows and 56 columns V6123 mux mode 8 with 8 rows and 52 columns Very simple 1-bit interface, reduced to its simplest form Frame frequency on chip by internal RC oscillator Voltage bias and mux signal generation on chip 1 display RAM addressable as 8 x 60 bit words Column driver only mode to have 60 column outputs No busy states No external components needed Blank function for LCD blanking Bit mapped Wide VDD voltage supply range, 2 to 6 V Wide VLCD voltage supply range, 2 to 8.5 V -40 to + 85 C temperature range
Fig. 1
Description
The V6123 is a low multiplex LCD driver. The 2, 4 and 8 way multiplex is digitally programmable by the command byte. The display refresh is handled on chip by an internal RC oscillator via 1 selectable 8 x 60 RAM which holds the LCD content driven by the driver. LCD pixels (or segments) are addressed on a one to one basis with the 8 x 60 bit RAM (a set bit corresponds to an activated LCD pixel). The V6123 has a very low dynamic current consumption, typically 175 A at VDD = 5 V, VLCD = 7 V, making it particularly attractive for portable and battery powered products. The wide operating range on supply voltages and tem perature offers much application flexibility. The LCD bias generation and frame frequency are generated on chip. The clock signal can be used to shift and to latch the data into the RAM.
Pad Assignment
Applications
n n n n n n n
Automotive displays Telephones Pagers Portable, battery operated products Large displays (public information panels, etc.) Balances and scales Utility meters
Fig. 2
1
V6123
Absolute Maximum Ratings
Parameter
Supply voltage range LCD supply voltage range Voltage at DI, DO, CLK, FR Voltage at V1 to V3, S1 to S60 Storage temperature range PElectrostatic discharge max. to MIL-STD-883C method 3015 Maximum soldering conditions
Handling Procedures
Conditions
This device has built-in protection against high static voltages or electric fields; however, anti-static precautions must be taken as for any other CMOS component. Unless otherwise specified, proper operation can only occur when all terminal voltages are kept within the supply voltage range. Unused inputs must always be tied to a de fined logic voltage level.
Symbol
VDD VLCD VLOGIC VDISP TSTO VSmax TSmax
-0.3 V to 9 V -0.3 V to 10 V -0.3 V to V DD +0.3 V -0.3 V to VLCD +0.3 V -65 to +150 C 1000 V 250 C x 10 s
Table 1 Stresses above these listed maximum ratings may cause permanent damage to the device. Exposure beyond specified operating conditions may affect device reliability or cause malfunction.
Operating Conditions
Parameter
Operating temperature Logic supply voltage LCD supply voltage
Symbol Min. Typ. Max. Unit
TA VDD VLCD -40 2 2 5 5 +85 6 8.5 C V V
Table 2
Electrical Characteristics
Parameter
Dynamic supply current Dynamic supply current Dynamic supply current Dynamic supply current Control Signals DI, CLK, FR Input leakage Input capacitance Low level input voltage High level input voltage Data Output DO High level output voltage Low level output voltage Driver Outputs S1 ... S60 Driver impedance 4) Driver impedance 4) Driver impedance 4) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 5) Bias impedance V1, V2, V3 5) DC output component
1) 2)
VDD = 5 V 10%, VLCD = 2 to 8.5 V and TA = -40 to +85 C, unless otherwise specified
Symbol Test Conditions
ILCD IDD IDD IDD IIN CIN VIL VIH VOH VOL ROUT ROUT ROUT RBIAS RBIAS RBIAS VDC See note See note 1) at T A = 25 C See note 1) See note 2)
1)
Min.
Typ.
175 29 29 285 1 8
Max.
250 35 50 350 100 0.8 VDD
Units
A A A A nA pF V V V V k k k k k k mV
0 < V IN < VDD at TA = 25 C
0 2.0 2.4
IH = 2 mA IL = 2 mA IOUT = 10 A, VLCD = 7 V IOUT = 10 A, VLCD = 3 V IOUT = 10 A, VLCD = 2 V IOUT = 10 A, VLCD = 7 V IOUT = 10 A, VLCD = 3 V IOUT = 10 A, VLCD = 2 V see Tables 4a and 4b, VLCD = 5 V
0.4 1 2.6 7 18 20 24 15 1.5 3.5 24 27 50
All outputs open, DI and CLK at VSS, FR = 400 Hz, all other inputs at VDD Table 3 All outputs open, DI at VSS, FR = 400 Hz, fCLK = 1 MHz 3) All outputs open, all inputs at VDD 4) This is the impedance between of the voltage bias level pins (V1, V2 or V3) and the output pins S1 to S60 when a given voltage bias level is driving the outputs (S1 to S60) 5) This is the impedance seen at the segment pin. Outputs measured one at a time
2
V6123
Column Drivers
Outputs
S1 to S60 S1 to S60 S1 to S60 S1 to S60
FR Polarity
logic 1 logic 0 logic 1 logic 0
Column Data
logic 1 logic 1 logic 0 logic 0
Measured
| Sx* - VSS | | VLCD - Sx* | | VLCD - Sx* | | Sx* - VSS |
Guaranteed
| VLCD - Sx* | = | Sx* - VSS | 25 mV | VLCD - Sx* | = | Sx* - VSS | 25 mV
*Sx = the output number (I.e. S1 to S60)
Table 4a
Row Drivers
Outputs
S1 to Sn* S1 to Sn* S1 to Sn* S1 to Sn*
FR Polarity
logic 1 logic 0 logic 1 logic 0
Row Data
logic 1 logic 1 logic 0 logic 0
Measured
| VLCD - Sx | | Sx - Vss | | Sx - VSS | | VLCD - Sx |
Guaranteed
| VLCD - Sx | = | Sx - VSS | 25 mV | VLCD - Sx | = | Sx - VSS | 25 mV
*n= the V6123 mux programme number (i.e. 2, 4 or 8)
Table 4b
Timing Characteristics
Parameter
Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width FR (internal frame frequency)
1) 2)
VDD = 5 V 10%, VLCD = 2 to 8.5 V, and TA = -40 C to +85 C
Symbol Test Conditions
tCH tCL tCR tCF tDS tDH tPD tSTR fFR2)
Min.
120 120 201) 301)
Typ.
Max.
2000 200 200 200
Units
ns ns ns ns ns ns ns s Hz
CLOAD = 50 pF TA = 25 C
6 45
55
65
tDS + tDH minimum must be 100 ns. If tDS = 20 ns then tDH 80 ns. V6123 n, FR = n times the desired LCD refresh rate where n is the V6123 mux mode number. See fig. 14, 15 for more details concerning frame frequency.
Table 5a
VDD = 2 to 6V, VLCD = 2 to 8.5 V, and TA = -40 C to +85 C
Parameter
Clock high pulse width Clock low pulse width Clock and FR rise time Clock and FR fall time Data input setup time Data input hold time Data output propagation STR pulse width
1)
Symbol Test Conditions
tCH tCL tCR tCF tDS tDH tPD tSTR
Min.
0.5 0.5 100 1) 150 1)
Typ.
Max.
1.5 200 200 500
Units
s s ns ns NS ns ns s
CLOAD = 50 pF
16
tDS + tDH minimum must be 500 ns. If tDS = 100 ns then tDH 400 ns.
Table 5b
3
V6123
Timing Waveforms
Fig. 3
Clock Definition
Fig. 4
Programmation Data Bits and Data Transfer Cycle
Command Bits 0 to 7 0 1 2 3 4 5 RAM Address Multiplex COL Ratio 6 7 Blank SET 0 0 0 1 1 Mux Ratio (bit 0, 1) 1 Mux Mode 0 2 1 4 0 1 8
Bit2: COL bit configure the V6123 function as row and column driver or column driver only. Bit 6: Blank bit forces all column outputs OFF. Bit 7: SET bit forces all column outputs ON.
Note: If bit 6 and 7 are both to 1L the chip is synchronized to row 1.
V6123 as a row and column driver, 68 bit load cycle, RAM address arising from command bits 3 to 5
Display RAM Address Command Bits 3 to 5 LCD Mux Mux Mux Row prog. 2 prog. 4 prog. 8 000 000 000 Row 1 001 001 001 Row 2 010 010 Row 3 011 011 Row 4 100 Row 5 101 Row 6 110 Row 7 111 Row 8 All mux mode programmation or COL states need 68 bit load cycles. Fig. 5 4
V6123
Block Diagram
10000000
Fig. 6
5
V6123
Pin Assignment
Name
S1 ... S60 V3 V2 V1 VLCD FR DI DO CLK VDD VSS
1)
Function
LCD outputs, see Table 7 LCD voltage bias level 3 1) 2) LCD voltage bias level 2 1) LCD voltage bias level 1 1) Power supply for the LCD AC I/O signal for LCD driver output Serial data input Serial data output Data clock input Power supply for logic Supply GND Table 6
Name
S1 S2 S3 S4 S5 S6 S7 S8 S9...S60
COL inactive
V6123 (2) V6123 (4) V6123 (8) Row1 Row1 Row1 Row2 Row2 Row2 Col1 Row3 Row3 Col2 Row4 Row4 Col3 Col1 Row5 Col4 Col2 Row6 Col5 Col3 Row7 Col6 Col4 Row8 Col7...58 Col5...56 Col1...52
COL active
Col1 Col2 Col3 Col4 Col5 Col6 Col7 Col8 Col9...60 Table 7
The V6123 has internal voltage bias level generation. When driving large pixels, an external resistor divider chain can be connnected to the voltage bias level inputs to obtain enhanced display contrast. See Fig. 11, 12 and 13. The external resistor divider ratio should be in accordance with the internal resistor ratio (see Table 8). 2) V3 is connected internally to V SS on the V6123 mux mode 4.
LCD Voltage Bias Levels
LCD Drive Type LCD Bias Configuration VOP3) VOFF (rms) VON (rms) VOFF (rms)
3)
VOP = V LCD - VSS
Table 8
6
V6123
Row and Column Multiplexing Waveform V6123 (2)
VOP = V LCD - VSS, VSTATE = VCOL - VROW
* See table 8
Fig. 7
7
V6123
Row and Column Multiplexing Waveform V6123 (4)
VOP = V LCD - VSS, VSTATE = VCOL - VROW
* See table 8
Fig. 8
8
V6123
Row and Column Multiplexing Waveform V6123 (8)
VOP = V LCD - VSS, VSTATE = VCOL - VROW
* See table 8
Fig. 9
9
V6123
Functional Description
The voltage between VDD and V SS is the supply voltage for the logic and the interface. The voltage between VLCD and VSS is the supply voltage for the LCD and is used for the generation of the internal LCD bias level which have a maximum impedance of 30 k for a voltage from 3 to 8.5 V. Without external connections to the V1, V2, V3 bias level inputs, the V6123 can drive most medium sized LCD (pixel aera up to 4'000 mm2). For displays with a wide variation in pixel sizes, the configuration shown in Fig. 12 can give enhanced contrast by giving faster pixel switching times. On changing the row polarity (see Fig. 7, 8 and 9) the parallel capacitors lower the impedance of the bias level generation to the peak current, giving faster pixel charge times and thus a higher RMS "on" value. A higher RMS "on" value can give better contrast. If for a given LCD size and operating voltage, the "off" pixels appear "on", or there is poor contrast, then an external bias level generation circuit can be used with the V6123. An external bias generation circuit can lower the bias level impedance and hence improve the LCD con trast (see Fig. 11). The optimum values of R, Rx and C, vary according to the LCD size used and VLCD. They are best determined through actual experimentation with the LCD. For LCD with very large average pixel area (eg. up to 10'000 mm2), the bias level configuration shown in Fig. 13 should be used. When V6123 are cascaded, connect the V1, V2 and V3 bias inputs as shown in Fig. 10. The pixel load is averaged across all the cascaded drivers. This will give en hanced display contrast as the effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6123 are cascaded as shown in Fig. 10, then the maximum bias level impedance becomes 15 k for a VLCD voltage from 3 to 8.5 V. Table 8 shows the relationship between V1, V2 and V3 for the multiplex rates 2, 4 and 8. Note that V LCD > V1 > V2 > V3 for the V6123 2 and 8 mux programmed, and for the V6123 4 mux programmed, VLCD > V1 > V2, and V3 = V SS.
Supply Voltage VLCD, VDD, VSS
The display RAM word length is 60 bits (see Fig. 6). Each LCD row has a corresponding display RAM address which provides the column data (on or off) when the row is selected (on). When down loading data to the V6123, any display RAM address can be chosen. Display RAM address is given by command bits 3 to 5. Bit 6 forces all column outputs at 0L (display OFF). Bit 7 forces all col umn outputs at 1L (display ON). If bit 7 (SET) and bit 6 (BLANK) are both active, the initialization function is activated. This function is used to synchronize the chip at row one. The command bit 2 (COL) defines the V6123 as a row and column driver or column driver only. The V6123 functions as row and column driver while the bit 2 (COL) is inactive. When active, the bit 2 configures the V6123 to function as column driver only. The former row outputs function as column outputs. In cascaded applications, one V6123 should be used in the row and column configuration (COL inactive) and the rest as pure column drivers (COL active) (see Fig. 10). Note when cascading V6123s never cascade one mux mode number with an other. If a V6123 8 mux programmed is used to drive the rows, then only V6123 8 mux programmed can be cas caded with it. The command bits, bit 1 and bit 0, define the mux mode (see Fig. 5).
CLK Input The clock input is used to clock the DI serial data into the shift register, to latch the data from the shift register into the RAM . After loading data into the shift register, the clock has to stay 0 logic during TSTR. After TSTR pulse, the data are latched into the RAM. FR Input / Output The frame frequency is realized by an internal RC oscillator with a typical value of 55 Hz. The internal row frequency changes with the number of rows (Frow = 55 x n, where n = 2, 4 or 8). When bit 2 (COL) is inactive (row and column driver), the frame frequency is given by the internal oscillator. This frequency can also be used at FR output to drive casecaded V6123. When bit 2 (COL) is active (column driver only), the frame frequency is external then the frequency is given by the row and column driver directly to the FR input. In cascaded applications, the row and column driver (FR, output) give the frame frequency to all the cascaded chip (FR, input). Driver Outputs S1 to S60 There are 60 LCD driver outputs on the V6123. When bit 2 (COL) is inactive, the outputs S1 to Sn function as row drivers and the outputs S(n+1) to S60 function as column drivers. Where n is the V6123 mux mode number (2, 4 or 8). When bit 2 (COL) is active, all 60 outputs function as column drivers (see Table 6). There is a one to one relationship between the display RAM and the LCD driver
Data Input / Output The data input pin, DI, is used to load serial data into the V6123. The serial data word length is 68 bits. Data is loaded in inverse numerical order, the data for bit 68 is loaded first, the data for bit 1 last. The column data bits are loaded first and then the command byte (see Fig. 5). The data output pin, DO, is used in cascaded application (see Fig. 10). DO transfers the data to the next cascaded chip. The data at DO is equal to the data at DI delayed by 68 clock periods. In order to cascade V6123s, the DO of one chip must be connected to DI of the following chip (see Fig. 10). In cascaded applications the data for the last V6123 (the one that does not have DO connected) must be loaded first and the data for the first V6123 (it is DI connected to the processor) loaded last. 10
V6123
outputs. Each pixel (segment) driven by the V6123 on the LCD has a display RAM bit which corresponds to it. Setting the bit turns the segment "on" and clearing it turns it "off".
Power-Up On power up the data in the shift registers, the display RAM, the sequencer driving the 2/4/8 rows and the 60 bit display latches are undefined.
Applications
Two V6123 8 Mux Programmed Cascaded
By connecting the V1, V2 and V3 bias inputs as shown, the pixel load is averaged across all the drivers. The effective bias level source impedance is the parallel combination of the total number of drivers. For example, if two V6123 are cascaded as above, then the maximum bias level impedance becomes 15 k. Fig. 10
V6123 8 Mux Programmed with External Resistor Divider Bias Generation
Example set values: R = 3.3 - 10 k C = 2.2 - 47 nF Rx is given by the formula: Rx = 4R ((VDISP/VLCD)-1) = 10 - 30 k
Fig. 11
11
V6123
Enhanced Switching from the V6123
Temperature compensation/ Contrast adjustment
Bias Configuration for Large LCD
Large LCD example: VOP = 5 V, average pixel active area = up to 10'000 mm2, displasy refresh rate = 55 Hz C = 1 F Rx is given by the formula: Rx = 4(24 k)((VDISP/VLCD) - 1) Fig. 12 For a single V6123 4 mux programmed driving such an LCD, the voltage follower buffer (opamp) requirement is: peak current 1.8 mA steady state current typically 150 A Fig. 13
Frame Frequency vs. Temperature at VDD = 4.5 V
Fig. 14 Frame Frequency vs. VDD at TA = 25C
Fig. 15 12
V6123
Application Example
This table shows how to use the V6123 with a given initialization for Chip-on-Glas. Rows "Data" show the logical value to affect pad DI for each falling edge of pad CLK. After loading data into the shift register, the clock has to stay logic 0 during tSTR. After the tSTR pulse the data are latched into the RAM.
Display Data
8 Bits "don't care"
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 00101XXXXXXXX Command Byte 76543210 00000111 Last send Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,0,0: data sent to row 1 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.01
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 0 0 0 0 1 1 0 0 0 1 0 0 0 1 0 00101XXXXXXXX Command Byte 76543210 00100111 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,0,1: data sent to row 2 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.02
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 0 0 0 1 1 1 0 0 0 1 0 0 0 1 0 00101XXXXXXXX Command Byte 76543210 00010111 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,1,0: data sent to row 3 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.03
Table 9 (continued on following pages)
13
V6123
Table 9 continued
Display Data
8 Bits "don't care"
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 1 1 0 0 0 1 0 1 1 1 0 0 1 1 0 00101XXXXXXXX Command Byte 76543210 00110111 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,1,1: data sent to row 4 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.04
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 00101XXXXXXXX Command Byte 76543210 00001111 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 =1,0,0: data sent to row 5 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.05
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 0 1 0 0 0 1 0 1 0 0 0 0 0 1 0 00101XXXXXXXX Command Byte 76543210 00101111 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 1,0,1: data sent to row 6 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.06
Table 9 (continued on next pages)
14
V6123
Table 9 continued Display Data 8 Bits "don't care"
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 1 1 0 0 0 1 0 1 1 1 0 1 1 1 0 00010XXXXXXXX Command Byte 76543210 00011111 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 1,1,0: data sent to row 7 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.07
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000XXXXXXXX Command Byte 76543210 00111111 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 1,1,1: data sent to row 8 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.08
Bit No 7 DATA 1
6 0
Command Byte 54321 11111
0 1
Bit 7,6 = 1,0: Bit 3 to 5 = 1,1,1: Bit 2 = 1: Bit 0,1 = 1,1:
SET, no blank data sent to row 8 of the RAM row and column driver configuration mux 8
Fig.16.09
Table 9 (continued on next pages)
15
V6123
Table 9 continued Display Data
Command Byte 654321 111111
8 Bits "don't care"
Bit No 7 Data 0
0 1
Bit 7,6 = 0,1: Bit 3 to 5 = 1,1,1: Bit 2 = 1: Bit 0,1 = 1,1:
no set, BLANK data sent to row 8 of the RAM row and column driver configuration mux 8
Fig.16.10
Bit No 7 Data 1
Command Byte 654321 100011
0 1
Bit 7,6 = 1,1: Bit 3 to 5 = 0,0,0: Bit 2 = 1: Bit 0,1 = 1,1:
no set, no blank Synchronize the chip at row 1 data sent to row 8 of the RAM, you have to rewrite row 8 of the RAM row and column driver configuration mux 8
Fig.16.11
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 00000XXXXXXXX Command Byte 76543210 11111111 Bit 7,6 = 1,1: no set, no blank Synchronize the chip at row 1 Bit 3 to 5 = 1,1,1: data sent to row 3 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 1,1: mux 8
Fig.16.12
Table 9 (continued on next pages)
16
V6123
Table 9 continued Display Data 8 Bits "don't care"
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 101010101XXXX Command Byte 76543210 00000110 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,0,0: data sent to row 1 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 0,1: mux 4
Fig.16.13
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 010101010XXXX Command Byte 76543210 00010110 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,0,1: data sent to row 2 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 0,1: mux 4
Fig.16.14
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 010101010XXXX Command Byte 76543210 00010110 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,1,0: data sent to row 3 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 0,1: mux 4
Fig.16.15
Table 9 (continued on next page)
17
V6123
Table 9 continued Display Data 8 Bits "don't care"
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 010101010XXXX Command Byte 76543210 00110110 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,1,1: data sent to row 4 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 0,1: mux 4
Fig.16.16
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 10101010101XX Command Byte 76543210 00000100 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,0,0: data sent to row 1 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 0,0: mux 2
Fig.16.17
Bit No 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 ... ... 20 19 18 17 16 15 14 13 12 11 10 9 8 DATA 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 10101010101XX Command Byte 76543210 00100100 Bit 7,6 = 0,0: no set, no blank Bit 3 to 5 = 0,0,1: data sent to row 2 of the RAM Bit 2 = 1: row and column driver configuration Bit 0,1 = 0,0: mux 2
Fig.16.18
Table 9
18
V6123
Package and Ordering Information
Dimensions of Chip Form
Thickness: Bump size: Chip size: Note:
11 mils typ. Output pad = 110 x 110 micron, Input pad = 120 x 120 micron [X x Y] 8864 x 1981 micron or 349 x 78 mils The origin (0,0) is the lower left coordinate of center pads. The lower left corner of the chip shows distances to origin.
Fig. 17
Ordering Information The V6123 is available in the following packages:
Chip form Bumped form V6123 Chip V6123 Bumped
When ordering please specify the complete part number and package.
EM Microelectronic-Marin SA cannot assume any responsibility for use of any circuitry described other than entirely embodied in an EM Microelectronic-Marin SA product. EM Microelectronic-Marin SA reserves the right to change the circuitry and specifications without notice at any time. You are strongly urged to ensure that the information given has not been superseded by a more up-to-date version.
E. & O.E. Printed in Switzerland, Th (c) 2000 EM Microelectronic-Marin SA, 07/00, Vers. D/301
EM Microelectronic-Marin SA, CH - 2074 Marin, Switzerland, Tel. (+41) 32 - 755 51 11, Fax (+41) 32 - 755 54 03 19

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